1. Technical Field
This invention relates generally to general-purpose integrated circuits and more particularly to integrated circuits having a plurality of serial transceivers.
2. Description of Related Art
As is known, integrated circuits (ICs) may be fabricated using a variety of technologies (e.g., CMOS, gallium arsenide, silicon germanium, bi-polar, etc.) to provide an endless list of electronic circuits. For example, microprocessors, read only memory (ROM), static random access memory (SRAM), dynamic random access memory (DRAM), field programmable gate arrays (FPGA), and digital signal processors (DSP) are typically fabricated using CMOS technology and provide vast programmable electronic circuits and/or data storage.
As the amount of data processed by such ICs increases and the time to process such data decreases, getting the data on to and off of the chip in sufficient amounts and in a timely manner presents an ever increasing IC design challenge. One common solution to this problem is to increase the width of the input and output interfaces of the IC. For instance, the data may be provided in parallel in 32 bit data words, 64 bit data words, etc. While this technique meets its objective, it requires the IC to a large number of pins to accommodate the large parallel inputs and outputs, which increases the IC package size, increases die size, adds cost, and makes IC and printed circuit board (PCB) layouts more difficult.
Another solution is to include high-speed serial interfaces on the IC. As is known, a high-speed serial interface transmits and receives a serial stream of data, thus requiring only one IC pin for the transmit path and one IC pin for the receive path. As is further known, a high-speed interface converts received serial data into parallel data to correspond to the internal bus size of the IC. In addition, a high-speed serial interface, or transceiver, converts transmit parallel data into transmit serial data. When such high-speed serial interfaces are implemented using CMOS technology, the rate of the serial data is somewhat limited. For example, a 3.125 Gigabit-per-second (Gbps) serial data rate is about the maximum rate for 0.18 micron CMOS technology.
To achieve data rates above a technology limitation (e.g., the 3.125 Gbps for 0.18 micron CMOS), several serial channels may be operated in parallel, which is referred to as channel bonding. For example, to achieve a 12.5 Gbps data rate, four 3.125 Gbps transceivers may be bonded together (i.e., 4*3.125=12.5). In this example, each transceiver processes ¼th of the data, which is done at the same time as the other transceivers are processing their respective fourths of the data.
The technical challenge with channel bonding is to insure that each transceiver stays in step with all of the other transceivers, such that the ordering of the data is not lost during the parallel processing. For instance, in the four transceiver example, a first transceiver processes the first of every four bits of the input or output serial data, a second transceiver processes the second of every four bits of the input or output serial data, a third transceiver processes the third of every four bits of the input or output serial data, and a fourth transceiver processes the fourth of every four bits of the input or output serial data. If this ordering is lost, even temporarily, the received or transmitted data will be corrupted.
Due to channel bonding set-up latencies (i.e., the processing time to recognize initiation of channel bonding, to adjust memory access timing, and to allocate responsibilities to the transceivers), the number of transceivers that can be bonded together are limited. Typically, only about four 3.125 Gbps transceivers can be bonded together due to set-up latencies. As the dies size increases, the spacing of the transceivers may also increase, which adds to the set-up latencies. Further, consumer demands for even higher data rates (e.g., 40 Gbps) are increasing.
Therefore, a need exists for a technique of bonding a significant number of channels (i.e., high-speed serial transceivers) to achieve high data rates without limitation due to set-up latencies.